Explore projects

My first RV32IZifencei implementation in Verilog using Quartus Prime as an ide

The Inextensible RISC-V Emulator

Autograder for ECE 350 :)

Paper: https://ieeexplore.ieee.org/document/10545398

Paper: https://ieeexplore.ieee.org/document/10545398

Paper: https://ieeexplore.ieee.org/document/10545398

Rust interpreter for iverilog compiled VVP target files.

Also potentially the start of an IEEE 1800 simulator in Rust.

Fixes for running Linux on the Lenovo Flex 5 14ARE15

ECE250 Testcases and Autograder

A neat x86 kernel/os written in good ol' c. And assembly. Oh boy, here we go...

Performant RISC-V Processing