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LETC
The Little Engine That Could (Run Linux) :)
Lore
LETC is the last step on our journey within the Angry Goose Initiative.
It is a 6-stage in-order pipelined RISC-V soft-core design, targeting the Cora Z7 devboard containing a Zync 7000 FPGA.
It will have TLBs, caches, a hardware page table walker, and will accesses peripherals and memory over an AXI interconnect of our own making!
If you're reading this, as of writing we're in a transition period between wrapping up IRVE, our C++ reference implementation, and beginning LETC. Exciting stuff!
For more details, and an overarching view of LETC's Architecture, visit this page.
EEI information (ie. the standards LETC implements) can be found here.
LETC is in part based on IRVE, JZJCoreF, and JZJPipelinedCoreC.
Okay enough backstory, I want to try this out!
Awesome!
If you want to simulate LETC, check out this wiki page.
If you want to synthesize LETC, or program it onto your own devboard, this is the page for you!
Want to run Linux on the thing? Check this out.