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My first RV32IZifencei implementation in Verilog using Quartus Prime as an ide

A neat x86 kernel/os written in good ol' c. And assembly. Oh boy, here we go...

The eXtensible RISC-V Emulator

VSmile EMUlator

"LEGv8" Instruction Set Tools (Minimized version of ARMv8 for my ECE 222 course)

A matrix/linear system solver written in C. You can probably tell I'm really enjoying MATH 115 :)

A web server dedicated to generating Mandelbrot images on the fly and making them available for download by visiting a particular link

My third RISC-V soft core cpu implementation (RV32IZifencei) with even lower cycles per instruction and an even higher fMax.

My 4th RISC-V cpu implementation with pipelining (RV32I)!

Second attempt at a pipelined cpu (RV32I w/ 5 stages)

Second RV32IZifencei soft core cpu implementation with higher performance

My fifth RISC-V soft core cpu implementation (RV32IZifencei) with an fMax that is even higher!

My 1st RISC-V cpu implementation with pipelining (RV32I)!

1st repo

Monolithic chess game for the terminal and the desktop!