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John Zacarias Jekel / jzjcorec
MIT LicenseMy third RISC-V soft core cpu implementation (RV32IZifencei) with even lower cycles per instruction and an even higher fMax.
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John Zacarias Jekel / jzjcored
MIT LicenseMy 4th RISC-V cpu implementation with pipelining (RV32I)!
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John Zacarias Jekel / jzjpipelinedcoreb
MIT LicenseSecond attempt at a pipelined cpu (RV32I w/ 5 stages)
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John Zacarias Jekel / jzjcoreb
MIT LicenseSecond RV32IZifencei soft core cpu implementation with higher performance
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John Zacarias Jekel / jzjcoree
MIT LicenseMy fifth RISC-V soft core cpu implementation (RV32IZifencei) with an fMax that is even higher!
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John Zacarias Jekel / jzjpipelinedcorea
MIT LicenseMy 1st RISC-V cpu implementation with pipelining (RV32I)!
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John Zacarias Jekel / jzjcoref
MIT LicenseA fast RV32IZifencei soft core implementation with a 2 stage pipeline(ish), written in SystemVerilog!
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John Zacarias Jekel / jzjcoresoftware
MIT LicenseContains software to run on JZJCoreX cores
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John Zacarias Jekel / compositestm32
MIT LicenseImport of STM32 composite code that I developed locally
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John Zacarias Jekel / chess
MIT LicenseArchived 0Updated -
John Zacarias Jekel / cheja
MIT LicenseMonolithic chess game for the terminal and the desktop!
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John Zacarias Jekel / checkers
MIT LicenseA classic game you can now play in the terminal!
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John Zacarias Jekel / baremetalbluepill
MIT LicenseBloat-less library/initialization routines needed to write in c for the blue pill arm dev board
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John Zacarias Jekel / atmegaclock
MIT LicenseAlarm clock with an atmega328p without any Arduino libraries
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John Zacarias Jekel / atmegaclock2
MIT LicenseA continuation of http://git.jekel.ca/JZJ/atmegaclock.
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