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jzjcoref

Project information

A fast RV32IZifencei soft core implementation with a 2 stage pipeline(ish), written in SystemVerilog!

94 Commits
2 Branches
7 Tags

README
MIT License

Created on

July 05, 2024

Copy SSH clone URLgit@git.jekel.ca:jzj/jzjcoref.git
Copy HTTPS clone URLhttps://git.jekel.ca/jzj/jzjcoref.git

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