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My 4th RISC-V cpu implementation with pipelining (RV32I)!

Second attempt at a pipelined cpu (RV32I w/ 5 stages)

Let's do this this time.

Second RV32IZifencei soft core cpu implementation with higher performance

My fifth RISC-V soft core cpu implementation (RV32IZifencei) with an fMax that is even higher!

My 1st RISC-V cpu implementation with pipelining (RV32I)!

A fast RV32IZifencei soft core implementation with a 2 stage pipeline(ish), written in SystemVerilog!

Contains software to run on JZJCoreX cores

The Jekel Fractal Engine

1st repo

Import of STM32 composite code that I developed locally

Monolithic chess game for the terminal and the desktop!

A classic game you can now play in the terminal!

Bloat-less library/initialization routines needed to write in c for the blue pill arm dev board

Alarm clock with an atmega328p without any Arduino libraries

A simple Rust library to translate from English to Pig Latin!

A continuation of http://git.jekel.ca/JZJ/atmegaclock.