jzj/sv-api
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
No description
9 commits 3 branches 0 tags 100 KiB
  • Rust 100%
Find a file
Exact
John Jekel 2caa2d99c0 Begin to overhaul error handling
2023-11-30 22:30:06 -05:00
examples/initial_experiments Improve thread safety 2023-11-30 22:30:02 -05:00
lib Begin to overhaul error handling 2023-11-30 22:30:06 -05:00
.gitignore Initial commit 2023-11-30 13:53:08 -05:00
Cargo.lock Initial commit 2023-11-30 13:53:08 -05:00
Cargo.toml Initial commit 2023-11-30 13:53:08 -05:00
README.md Initial commit 2023-11-30 13:53:08 -05:00

README.md

sv-api

Idiomatic Rust abstractions and raw bindings for the SystemVerilog DPI, PLI, and VPI interfaces.

This crate is in a early development stage at the moment as I flesh out the goals of the project, but it will improve with time :)

TODO describe distinction between this and librstb (or perhaps even reuse parts of that)

  • Unlike librstb we're not focused on writing tests (assuming those will be written in SystemVerilog, potentially leveraging UVM, in the simulator)
  • Instead our focus is on simply providing a good abstraction to control a simulation, as well as retrieve data from it