JZJ synced commits to cache_design at JZJ/letc from mirror
- 797956da62 Fix write invalidation and improve cache tb
2 weeks ago
JZJ synced new reference personal/jzj/cachetest to JZJ/letc from mirror
2 weeks ago
JZJ synced commits to main at JZJ/letc from mirror
- 797956da62 Fix write invalidation and improve cache tb
- 5e59a1d3d1 Tweaks and fixes to `letc_core_cache`
- 1628fc14b7 first crack at write through
- b0c6386be5 small style changes to appease linter
- 02aa43cb09 add default cases to fsm, tie flush low in tb
- Compare 13 commits »
2 weeks ago
JZJ synced commits to staging at JZJ/letc from mirror
- 797956da62 Fix write invalidation and improve cache tb
- 5e59a1d3d1 Tweaks and fixes to `letc_core_cache`
- 1628fc14b7 first crack at write through
- b0c6386be5 small style changes to appease linter
- 02aa43cb09 add default cases to fsm, tie flush low in tb
- Compare 12 commits »
2 weeks ago
JZJ synced new reference personal/jzj/axi_fsm_tweaks to JZJ/letc from mirror
2 weeks ago
JZJ synced commits to personal/jzj/primary at JZJ/letc from mirror
- 1174208b96 !!!INPROGRESS!!! Fix TGHM for base spec instructions
- 97bab5fab5 Implement much of the TGHM
- 06a2f9371f AXI FSM Fixes
- Compare 3 commits »
2 weeks ago
JZJ synced commits to personal/ej/mem_ip_experiments at JZJ/letc from mirror
- 30a6fc426b tied off extra axi_fsm limp signals
- 7e82d02be7 fleshed out testbench, making requests
- 45308e58c5 added generated IP and beginnings of test bench
- a30909ac0b first crack at write through
- b86dbe81ee small style changes to appease linter
- Compare 20 commits »
2 weeks ago
JZJ synced commits to personal/jzj/primary at JZJ/letc from mirror
- cbc0468f06 !!!INPROGRESS!!! Fix TGHM for base spec instructions
2 weeks ago
JZJ synced commits to personal/jzj/primary at JZJ/letc from mirror
- 053e5988a7 Implement much of the TGHM
- c37ac65c30 Add skeletons for the GPIO and SRAM peripherals
- Compare 2 commits »
4 weeks ago
JZJ synced commits to cache_design at JZJ/letc from mirror
- 5e59a1d3d1 Tweaks and fixes to `letc_core_cache`
- 1628fc14b7 first crack at write through
- b0c6386be5 small style changes to appease linter
- 02aa43cb09 add default cases to fsm, tie flush low in tb
- f9fe76da3d Update regression to add new common modules!
- Compare 12 commits »
4 weeks ago
JZJ synced new reference peripherals_beginning to JZJ/letc from mirror
4 weeks ago
JZJ synced commits to staging at JZJ/letc from mirror
- c37ac65c30 Add skeletons for the GPIO and SRAM peripherals
4 weeks ago
JZJ synced commits to cache_design at JZJ/letc from mirror
- 46c1ad2483 Tweaks and fixes to `letc_core_cache`
- f8f79aae98 first crack at write through
- 77d9635a2e small style changes to appease linter
- ff55129b67 add default cases to fsm, tie flush low in tb
- 1569d571ba Update regression to add new common modules!
- Compare 17 commits »
4 weeks ago
JZJ synced commits to main at JZJ/letc from mirror
- 276b436fd3 Translate the `pc_word` signal in `e1` into a byte address
- dd696a2e8d Update LICENSE :)
- ee20aa08d5 Implement the rest of F1 except for the TLB, I think...
- d0ce713bfe Added PC word flip flop
- 4327ca3c1e Added basci multiplexer functionality
- Compare 28 commits »
4 weeks ago
JZJ synced commits to personal/jzj/primary at JZJ/letc from mirror
- 262a8e506f !!!TEMP!!! branch hazard fixes in progress
- 590df99939 Implement much of the TGHM
- 276b436fd3 Translate the `pc_word` signal in `e1` into a byte address
- dd696a2e8d Update LICENSE :)
- ee20aa08d5 Implement the rest of F1 except for the TLB, I think...
- Compare 6 commits »
4 weeks ago
JZJ synced commits to staging at JZJ/letc from mirror
- 276b436fd3 Translate the `pc_word` signal in `e1` into a byte address
- dd696a2e8d Update LICENSE :)
- ee20aa08d5 Implement the rest of F1 except for the TLB, I think...
- d0ce713bfe Added PC word flip flop
- 4327ca3c1e Added basci multiplexer functionality
- Compare 5 commits »
4 weeks ago
JZJ synced commits to personal/ej/cache_fsm at JZJ/letc from mirror
- 33218310d0 first crack at write through
1 month ago