John Zacarias Jekel JZJ
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Zacore
SystemVerilog 0 0

Performant RISC-V Processing

Updated 1 year ago

VSEMUR
Rust 1 0

VSmile EMUlator in Rust

Updated 1 year ago

VSEMU
Archived
C 0 0

VSmile EMUlator

Updated 2 years ago

TodoOS
Archived
Assembly 0 0

A neat x86 kernel/os written in good ol' c. And assembly. Oh boy, here we go...

Updated 2 years ago

testing-how-to-make-a-repo-on-gitlab
Archived
0 0

Updated 2 years ago

stm32basic
C 1 0

Basic interpreter (PS2 Keyboard and composite) using 2 stm32f103c8t6 mcus.

Updated 2 years ago

matrixmangler
Archived
C 0 0

A matrix/linear system solver written in C. You can probably tell I'm really enjoying MATH 115 :)

Updated 2 years ago

jzjpipelinedcorec
SystemVerilog 0 0

Let's do this this time.

Updated 2 years ago

jzjpipelinedcoreb
Archived
SystemVerilog 0 0

Second attempt at a pipelined cpu (RV32I w/ 5 stages)

Updated 2 years ago

jzjpipelinedcorea
Archived
Verilog 0 0

My 1st RISC-V cpu implementation with pipelining (RV32I)!

Updated 2 years ago

jzjcoresoftware
Assembly 0 0

Contains software to run on JZJCoreX cores

Updated 2 years ago

jzjcoref
SystemVerilog 1 0

A fast RV32IZifencei soft core implementation with a 2 stage pipeline(ish), written in SystemVerilog!

Updated 2 years ago

jzjcoree
Archived
Verilog 0 0

My fifth RISC-V soft core cpu implementation (RV32IZifencei) with an fMax that is even higher!

Updated 2 years ago

jzjcored
Archived
Verilog 0 0

My 4th RISC-V cpu implementation with pipelining (RV32I)!

Updated 2 years ago

jzjcorec
Archived
Verilog 0 0

My third RISC-V soft core cpu implementation (RV32IZifencei) with even lower cycles per instruction and an even higher fMax.

Updated 2 years ago