A small core implementing a custom ISA running on the same clock as a VGA driver. Written in SV, with the purpose of refreshing myself on how to use the HDL (I'm a bit rusty :))

Updated 2 years ago

Updated 2 years ago

A fast RV32IZifencei soft core implementation with a 2 stage pipeline(ish), written in SystemVerilog!

Updated 2 years ago

Second attempt at a pipelined cpu (RV32I w/ 5 stages)

Updated 2 years ago

Let's do this this time.

Updated 2 years ago

Performant RISC-V Processing

Updated 1 year ago

The Little Engine That Could (Run Linux) :)

Updated 2 weeks ago