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JZJ / letc

SystemVerilog 0 0

The Little Engine That Could (Run Linux) :)

Updated 4 months ago

JZJ / Zacore

SystemVerilog 0 0

Performant RISC-V Processing

Updated 1 year ago

JZJ / jzjpipelinedcorec

SystemVerilog 0 0

Let's do this this time.

Updated 1 year ago

JZJ / jzjpipelinedcoreb

Archived

SystemVerilog 0 0

Second attempt at a pipelined cpu (RV32I w/ 5 stages)

Updated 1 year ago

JZJ / jzjcoref

SystemVerilog 1 0

A fast RV32IZifencei soft core implementation with a 2 stage pipeline(ish), written in SystemVerilog!

Updated 1 year ago

JZJ / cycloneivvgasoftrenderer

Archived

SystemVerilog 0 0

Updated 1 year ago

JZJ / vgacpu

SystemVerilog 1 0

A small core implementing a custom ISA running on the same clock as a VGA driver. Written in SV, with the purpose of refreshing myself on how to use the HDL (I'm a bit rusty :))

Updated 1 year ago