Basic interpreter (PS2 Keyboard and composite) using 2 stm32f103c8t6 mcus.

Updated 2 years ago

A matrix/linear system solver written in C. You can probably tell I'm really enjoying MATH 115 :)

Updated 2 years ago

Let's do this this time.

Updated 2 years ago

Second attempt at a pipelined cpu (RV32I w/ 5 stages)

Updated 2 years ago

My 1st RISC-V cpu implementation with pipelining (RV32I)!

Updated 2 years ago

Contains software to run on JZJCoreX cores

Updated 2 years ago

A fast RV32IZifencei soft core implementation with a 2 stage pipeline(ish), written in SystemVerilog!

Updated 2 years ago

My fifth RISC-V soft core cpu implementation (RV32IZifencei) with an fMax that is even higher!

Updated 2 years ago

My 4th RISC-V cpu implementation with pipelining (RV32I)!

Updated 2 years ago

My third RISC-V soft core cpu implementation (RV32IZifencei) with even lower cycles per instruction and an even higher fMax.

Updated 2 years ago

Second RV32IZifencei soft core cpu implementation with higher performance

Updated 2 years ago

My first RV32IZifencei implementation in Verilog using Quartus Prime as an ide

Updated 2 years ago

Updated 2 years ago

Import of STM32 composite code that I developed locally

Updated 2 years ago

Bloat-less library/initialization routines needed to write in c for the blue pill arm dev board

Updated 2 years ago

A continuation of http://git.jekel.ca/JZJ/atmegaclock.

Updated 2 years ago

Alarm clock with an atmega328p without any Arduino libraries

Updated 2 years ago

1st repo

Updated 2 years ago

An almost identical port of 15Slide to Java 11.

Updated 2 years ago