Idiomatic Rust abstractions and raw bindings for the SystemVerilog DPI, PLI, and VPI interfaces.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
John Jekel 2caa2d99c0 Begin to overhaul error handling 7 months ago
examples/initial_experiments Improve thread safety 7 months ago
lib Begin to overhaul error handling 7 months ago
.gitignore Initial commit 7 months ago
Cargo.lock Initial commit 7 months ago
Cargo.toml Initial commit 7 months ago
README.md Initial commit 7 months ago

README.md

sv-api

Idiomatic Rust abstractions and raw bindings for the SystemVerilog DPI, PLI, and VPI interfaces.

This crate is in a early development stage at the moment as I flesh out the goals of the project, but it will improve with time :)

TODO describe distinction between this and librstb (or perhaps even reuse parts of that)

  • Unlike librstb we're not focused on writing tests (assuming those will be written in SystemVerilog, potentially leveraging UVM, in the simulator)
  • Instead our focus is on simply providing a good abstraction to control a simulation, as well as retrieve data from it