Commit Graph

156 Commits (main)
 

Author SHA1 Message Date
John Zacarias Jekel 797956da62 Fix write invalidation and improve cache tb 2 weeks ago
John Zacarias Jekel 5e59a1d3d1 Tweaks and fixes to `letc_core_cache` 4 weeks ago
Eric Jessee 1628fc14b7 first crack at write through 4 weeks ago
Eric Jessee b0c6386be5 small style changes to appease linter 4 weeks ago
Eric Jessee 02aa43cb09 add default cases to fsm, tie flush low in tb 4 weeks ago
John Zacarias Jekel f9fe76da3d Update regression to add new common modules! 4 weeks ago
Eric Jessee 48f2f37379 added parallel load to shift register 4 weeks ago
Eric Jessee 1a61e0561a some cleanup and organization of fsm logic 4 weeks ago
Eric Jessee 76df022ecc first crack at refill machinery 4 weeks ago
Eric Jessee 7c1d469b66 added counter 4 weeks ago
Eric Jessee 5f2dd772a1 added shift register 4 weeks ago
Eric Jessee 26cd59016b added sketch of line refilling fsm 4 weeks ago
John Zacarias Jekel c37ac65c30 Add skeletons for the GPIO and SRAM peripherals 4 weeks ago
John Zacarias Jekel 276b436fd3 Translate the `pc_word` signal in `e1` into a byte address 4 weeks ago
John Zacarias Jekel dd696a2e8d Update LICENSE :) 4 weeks ago
John Zacarias Jekel ee20aa08d5 Implement the rest of F1 except for the TLB, I think... 4 weeks ago
s d0ce713bfe Added PC word flip flop 4 weeks ago
s 4327ca3c1e Added basci multiplexer functionality 1 month ago
Sam Graham 93fed1f2e7 Add LETC core Stage W rd_mux and op access comparison 1 month ago
John Zacarias Jekel fbd27cbd0b Update amd_lutram to add byte enables 1 month ago
John Zacarias Jekel ceeffc6d70 Implement hit/read logic 1 month ago
John Zacarias Jekel 2a7ea8e954 Add test infastructure for letc_core_cache 1 month ago
John Zacarias Jekel 1a390fda09 Begin to structure the cache (many things left to implement) 1 month ago
John Zacarias Jekel 255a59d773 Add an amd_lutram module, which may be useful :) 1 month ago
John Zacarias Jekel 2b0b43cf62 Remove letc_core_cache_if since we're just using LIMP 1 month ago
John Zacarias Jekel 5e6cbbe7c3 Tweak cache interface 1 month ago
John Zacarias Jekel ef5292ce10 Improve stubbing-out of the f2 and e2 stages 1 month ago
Eric Jessee 478afa07a0 remove ALU_OP_DO_NOTHING 1 month ago
Eric Jessee 8cc99c86e4 add to lint flow, and hook up bypass in core top 1 month ago
Eric Jessee 07d823b86c rename testbench to match module name 1 month ago
Eric Jessee 4d646715c9 improved naming convention 1 month ago
Eric Jessee be97950538 Implemented input muxing, more testbench cases (#5) 1 month ago
Eric Jessee 030b450b5b Early steps to ALU integration -- hard wire operands and op 1 month ago
Eric Jessee 0181c04ba4 beginnings of e1 testbench 1 month ago
John Zacarias Jekel 47be04d258 Improve things at LETC Core / the LETC top level 2 months ago
John Zacarias Jekel 7467144cb8 Improve Stage D testbench and fix bugs 2 months ago
John Zacarias Jekel 42ebc22442 Lint verif testbenches as well now too! 2 months ago
John Zacarias Jekel 40a7f1c15b Implement the bare basics of the decode stage 2 months ago
John Zacarias Jekel 0ce5be4dc2 Sort out ALU operands 2 months ago
John Zacarias Jekel a5f77d9de9 CSR interface fixes, and more decode work 2 months ago
John Zacarias Jekel 8b0335aeeb Add regression script for synthesis 2 months ago
John Zacarias Jekel 791bff4897 Lint with Verible in addition to svlint to catch more problems 2 months ago
John Zacarias Jekel 318de5931e Setup lint and fix fullchip synthesis 2 months ago
John Zacarias Jekel b5af77f910 Connect branch signals from D to F1 2 months ago
John Zacarias Jekel 164f827337 Skeleton interfaces between stages and caches/tlbs 2 months ago
John Zacarias Jekel a59e49c6bd Better organize the LIMP interface 2 months ago
John Zacarias Jekel 2e91ac9fe6 Migrate CSR module from the summer over to new dir structure 2 months ago
John Zacarias Jekel 7ef0d7c080 Add initial skeleton for caches, MMU, and TLBs 2 months ago
John Zacarias Jekel 1b4d80ffbc Add starting skeleton for TGHM 2 months ago
John Zacarias Jekel c50954507b Initial skeleton for LETC Core datapath 2 months ago