Lint with Verible in addition to svlint to catch more problems

pull/2/head
John Zacarias Jekel 2 months ago
parent 318de5931e
commit 791bff4897
  1. 24
      .github/workflows/lint.yml
  2. 30
      .github/workflows/verible_pr_review.yml
  3. 18
      .rules.verible_lint
  4. 13
      lint/verible.sh
  5. 4
      rtl/common/axi/axi_if.sv
  6. 2
      rtl/common/fifo/fifo_0r0w.sv
  7. 2
      rtl/common/fifo/fifo_0r1w.sv
  8. 2
      rtl/common/fifo/fifo_1r1w.sv
  9. 4
      rtl/letc/core/letc_core_axi_fsm.sv
  10. 2
      rtl/letc/core/letc_core_cache_if.sv
  11. 2
      rtl/letc/core/letc_core_limp_if.sv
  12. 2
      rtl/letc/core/letc_core_rf.sv
  13. 2
      rtl/letc/core/letc_core_stage_f1.sv
  14. 2
      rtl/letc/core/letc_core_stage_w.sv
  15. 2
      rtl/letc/core/letc_core_tlb.sv
  16. 2
      rtl/letc/core/letc_core_tlb_if.sv
  17. 2
      rtl/letc/letc_top.sv
  18. 3
      rtl/letc/matrix/letc_matrix_top.sv

@ -43,3 +43,27 @@ jobs:
run: |
. "$HOME/.cargo/env"
./svlint.sh
verible:
strategy:
fail-fast: false
matrix:
#We only support Linux
os: [ubuntu-latest]
runs-on: ${{ matrix.os }}
steps:
- uses: actions/checkout@master
- name: Install Verible Dependencies
shell: bash
run: |
sudo apt-get update -qq
sudo apt-get -y install --no-install-recommends git python3 python3-click python3-unidiff
- name: Install Verible
uses: chipsalliance/verible-actions-common/install-verible@main
with:
github_token: ${{ secrets.GITHUB_TOKEN }}
- name: Run Verible Lint
working-directory: ${{github.workspace}}/lint
run: |
./verible.sh

@ -0,0 +1,30 @@
name: Verible PR Review
#Thanks https://stackoverflow.com/questions/57699839/github-actions-how-to-target-all-branches-except-master
on:
pull_request:
branches: [ "**", "!legacy" ]
jobs:
verible_pr_lint:
runs-on: ubuntu-latest
permissions:
pull-requests: write
steps:
- uses: actions/checkout@master
- uses: chipsalliance/verible-linter-action@main
with:
config_file: '.rules.verible_lint'
paths: |
./rtl
exclude_paths: |
./rtl/fpga_wrapper
./rtl/legacy
extensions: |
.sv
.v
.vh
.svh
github_token: ${{ secrets.GITHUB_TOKEN }}
#TODO also verible format

@ -0,0 +1,18 @@
+line-length=length:120
-struct-union-name-style
-explicit-parameter-storage-type
-explicit-function-lifetime
-unpacked-dimensions-range-ordering
-case-missing-default
+endif-comment
+legacy-genvar-declaration
+proper-parameter-declaration
+signal-name-style
+suspicious-semicolon
+mismatched-labels
+numeric-format-string-style
+one-module-per-file
+typedef-structs-unions=allow_anonymous_nested:true
+uvm-macro-semicolon
+disable-statement
+forbid-negative-array-dim

@ -0,0 +1,13 @@
#!/bin/bash
# Copyright (C) 2024 John Jekel
# See the LICENSE file at the root of the project for licensing info.
#
# Lint All The Things!
#
# Should be run from the lint directory
# Exit on error immediately
set -e
cd ..
grep -o '^[^#]*' lint/filelist.f | xargs verible-verilog-lint --rules_config .rules.verible_lint

@ -261,13 +261,13 @@ assert property (@(posedge i_aclk) disable iff (!i_arst_n) wvalid |-> (wvalid t
assert property (@(posedge i_aclk) disable iff (!i_arst_n) bvalid |-> (bvalid throughout bready[->1]));
assert property (@(posedge i_aclk) disable iff (!i_arst_n) arvalid |-> (arvalid throughout arready[->1]));
assert property (@(posedge i_aclk) disable iff (!i_arst_n) rvalid |-> (rvalid throughout rready[->1]));
`endif
`endif //VERILATOR
//Stable while valid
//TODO
//TODO others
`endif
`endif //SIMULATION
endinterface : axi_if

@ -118,6 +118,6 @@ assert property (@(posedge i_clk) disable iff (!i_rst_n) !(i_pop & o_empty));
assert property (@(posedge i_clk) disable iff (!i_rst_n) !(push_idx >= (AWIDTH)'(DEPTH)));
assert property (@(posedge i_clk) disable iff (!i_rst_n) !(pop_idx >= (AWIDTH)'(DEPTH)));
`endif
`endif //SIMULATION
endmodule : fifo_0r0w

@ -111,6 +111,6 @@ assert property (@(posedge i_clk) disable iff (!i_rst_n) !(i_pop & o_empty));
assert property (@(posedge i_clk) disable iff (!i_rst_n) !(push_idx >= (AWIDTH)'(DEPTH)));
assert property (@(posedge i_clk) disable iff (!i_rst_n) !(pop_idx >= (AWIDTH)'(DEPTH)));
`endif
`endif //SIMULATION
endmodule : fifo_0r1w

@ -113,6 +113,6 @@ assert property (@(posedge i_clk) disable iff (!i_rst_n) !(i_pop & o_empty));
assert property (@(posedge i_clk) disable iff (!i_rst_n) !(push_idx >= (AWIDTH)'(DEPTH)));
assert property (@(posedge i_clk) disable iff (!i_rst_n) !(pop_idx >= (AWIDTH)'(DEPTH)));
`endif
`endif //SIMULATION
endmodule : fifo_1r1w

@ -51,7 +51,7 @@ word_t [NUM_REQUESTORS-1:0] limp_rdata;
word_t [NUM_REQUESTORS-1:0] limp_wdata;
generate
for (genvar ii = 0; ii < NUM_REQUESTORS; ++ii) begin : breakout_limp
for (genvar ii = 0; ii < NUM_REQUESTORS; ++ii) begin : g_breakout_limp
always_comb begin
limp_valid[ii] = limp[ii].valid;
limp[ii].ready = limp_ready[ii];
@ -61,7 +61,7 @@ for (genvar ii = 0; ii < NUM_REQUESTORS; ++ii) begin : breakout_limp
limp[ii].rdata = limp_rdata[ii];
limp_wdata[ii] = limp[ii].wdata;
end
end : breakout_limp
end : g_breakout_limp
endgenerate
/* ------------------------------------------------------------------------------------------------

@ -56,6 +56,6 @@ modport cache (
//TODO
`endif
`endif //SIMULATION
endinterface : letc_core_cache_if

@ -77,6 +77,6 @@ modport axi_fsm (
//TODO
`endif
`endif //SIMULATION
endinterface : letc_core_limp_if

@ -118,6 +118,6 @@ end
//TODO
`endif
`endif //SIMULATION
endmodule : letc_core_rf

@ -99,6 +99,6 @@ assign next_seq_pc = {next_seq_pc_word, 2'h0};
//TODO also in simulation init registers to 32'hDEADBEEF to aid debugging
`endif
`endif //SIMULATION
endmodule : letc_core_stage_f1

@ -44,6 +44,6 @@ module letc_core_stage_w
input e2_to_w_s i_e2_to_w
);
logic TODO;
logic todo;
endmodule : letc_core_stage_w

@ -26,6 +26,6 @@ module letc_core_tlb
//TODO design TLB interface to MMU
);
logic TODO;
logic todo;
endmodule : letc_core_tlb

@ -56,6 +56,6 @@ modport tlb (
//TODO
`endif
`endif //SIMULATION
endinterface : letc_core_tlb_if

@ -89,6 +89,6 @@ letc_matrix_top matrix (
//TODO
`endif
`endif //SIMULATION
endmodule : letc_top

@ -23,7 +23,8 @@ module letc_matrix_top
//AXI ports
axi_if.subordinate core,//Pre-buffered
axi_if.manager ps_gp,//Buffered//FIXME this too
axi_if.manager ps_acp,//Buffered//FIXME width needs to be converted to 64-bit, not in the switch but in another submodule under top; override the data and id widths
//FIXME width needs to be converted to 64-bit, not in the switch but in another submodule under top; override the data and id widths
axi_if.manager ps_acp,//Buffered
axi_if.manager aclint//Buffered
//TODO more as nesessary
);

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