Setup lint and fix fullchip synthesis

- Uses the `svlint` tool
- Still want to setup xsim and vsim linting too
- Need to fix Verilator lint errors that don't show up in sim but do here...
pull/2/head
John Zacarias Jekel 2 months ago
parent b5af77f910
commit 318de5931e
  1. 45
      .github/workflows/lint.yml
  2. 47
      .svlint.toml
  3. 1
      README.md
  4. 43
      lint/filelist.f
  5. 13
      lint/svlint.sh
  6. 13
      lint/verilator.sh
  7. 10
      rtl/common/axi/axi_buffer.sv
  8. 4
      rtl/common/fifo/fifo_0r0w.sv
  9. 2
      rtl/common/fifo/fifo_0r1w.sv
  10. 2
      rtl/common/fifo/fifo_1r1w.sv
  11. 2
      rtl/fpga_wrapper/coraz7_top.sv
  12. 2
      rtl/letc/core/letc_core_cache.sv
  13. 45
      rtl/letc/core/letc_core_csr.sv
  14. 2
      rtl/letc/core/letc_core_mmu.sv
  15. 4
      rtl/letc/core/letc_core_pkg.sv
  16. 2
      rtl/letc/core/letc_core_rf.sv
  17. 2
      rtl/letc/core/letc_core_stage_e2.sv
  18. 6
      rtl/letc/core/letc_core_stage_w.sv
  19. 8
      rtl/letc/core/letc_core_top.sv
  20. 2
      rtl/letc/matrix/letc_matrix_switch.sv
  21. 10
      synth/fc/fc_synth.tcl

@ -0,0 +1,45 @@
name: LETC Lint
#Thanks https://stackoverflow.com/questions/57699839/github-actions-how-to-target-all-branches-except-master
on:
push:
branches: [ "**", "!legacy" ]
pull_request:
branches: [ "**", "!legacy" ]
jobs:
svlint:
strategy:
fail-fast: false
matrix:
#We only support Linux
os: [ubuntu-latest]
runs-on: ${{ matrix.os }}
timeout-minutes: 120
steps:
- uses: actions/checkout@v3
- name: Cache svlint Installation
id: cache-svlint
uses: actions/cache@v3
env:
cache-name: cache-svlint-installation
with:
path: ~/.cargo
key: ${{runner.os}}-build-${{env.cache-name}}
- if: ${{ steps.cache-svlint.outputs.cache-hit != 'true' }}
name: Install svlint Compile Dependencies
run: sudo apt-get install cargo
- if: ${{ steps.cache-svlint.outputs.cache-hit != 'true' }}
name: Compile svlint
run: cargo install svlint
- name: Run svlint
working-directory: ${{github.workspace}}/lint
run: |
. "$HOME/.cargo/env"
./svlint.sh

@ -0,0 +1,47 @@
# .svlint.toml
# Copyright (C) 2024 John Jekel
# See the LICENSE file at the root of the project for licensing info.
#
# svlint configuration file for LETC
[option]
prefix_input = "i_"
prefix_output = "o_"
[textrules]
style_directives = true
style_semicolon = true
#style_indent = true
[syntaxrules]
action_block_with_side_effect = true
blocking_assignment_in_always_at_edge = true
blocking_assignment_in_always_ff = true
blocking_assignment_in_always_latch = true
#default_nettype_none = true#Vivado is incompatible with this
enum_with_type = true
function_same_as_system_function = true
general_always_level_sensitive = true
general_always_no_edge = true
genvar_declaration_in_loop = true
interface_port_with_modport = true
keyword_forbidden_always = true
keyword_forbidden_always_latch = true
keyword_forbidden_wire_reg = true
keyword_required_generate = true
#localparam_explicit_type = true#Honestly not that important
loop_variable_declaration = true
module_nonansi_forbidden = true
multiline_for_begin = true
multiline_if_begin = true
non_blocking_assignment_in_always_comb = true
non_blocking_assignment_in_always_no_edge = true
operator_case_equality = true
package_item_not_in_package = true
#parameter_explicit_type = true#Honestly not that important
procedural_continuous_assignment = true
prefix_input = true
prefix_output = true
#The space ones are too aggressive
style_trailingwhitespace = true
tab_character = true

@ -3,6 +3,7 @@
The Little Engine That Could (Run Linux) :)
[![LETC Non-UVM Tests](https://github.com/angry-goose-initiative/letc/actions/workflows/nonuvm_tests.yml/badge.svg?branch=main)](https://github.com/angry-goose-initiative/letc/actions/workflows/nonuvm_tests.yml)
[![LETC Lint](https://github.com/angry-goose-initiative/letc/actions/workflows/lint.yml/badge.svg?branch=main)](https://github.com/angry-goose-initiative/letc/actions/workflows/lint.yml)
## Lore

@ -0,0 +1,43 @@
# filelist.f
# Copyright (C) 2024 John Jekel
# See the LICENSE file at the root of the project for licensing info.
#
# Lint file list
rtl/common/fifo/fifo_0r0w.sv
rtl/common/fifo/fifo_0r1w.sv
rtl/common/fifo/fifo_1r1w.sv
rtl/common/cdc/cdc_synchronizer.sv
rtl/common/axi/axi_pkg.sv
rtl/common/axi/axi_if.sv
rtl/common/axi/axi_buffer.sv
rtl/letc/letc_pkg.sv
rtl/letc/letc_top.sv
rtl/letc/core/letc_core_pkg.sv
rtl/letc/core/letc_core_top.sv
rtl/letc/core/letc_core_rf.sv
rtl/letc/core/letc_core_stage_f1.sv
rtl/letc/core/letc_core_stage_f2.sv
rtl/letc/core/letc_core_stage_d.sv
rtl/letc/core/letc_core_stage_e1.sv
rtl/letc/core/letc_core_stage_e2.sv
rtl/letc/core/letc_core_stage_w.sv
rtl/letc/core/letc_core_tghm.sv
rtl/letc/core/letc_core_cache.sv
rtl/letc/core/letc_core_tlb.sv
rtl/letc/core/letc_core_mmu.sv
rtl/letc/core/letc_core_csr.sv
rtl/letc/core/letc_core_limp_if.sv
rtl/letc/core/letc_core_cache_if.sv
rtl/letc/core/letc_core_tlb_if.sv
rtl/letc/core/letc_core_axi_fsm.sv
rtl/letc/matrix/letc_matrix_top.sv
rtl/letc/matrix/letc_matrix_switch.sv
rtl/letc/matrix/letc_matrix_default_subordinate.sv
#We have to break convention here since we interact with AMD IP
#TODO fine-grained waivers
#rtl/fpga_wrapper/coraz7_top.sv

@ -0,0 +1,13 @@
#!/bin/bash
# Copyright (C) 2024 John Jekel
# See the LICENSE file at the root of the project for licensing info.
#
# Lint All The Things!
#
# Should be run from the lint directory
# Exit on error immediately
set -e
cd ..
svlint -D SIMULATION -f lint/filelist.f

@ -0,0 +1,13 @@
#!/bin/bash
# Copyright (C) 2024 John Jekel
# See the LICENSE file at the root of the project for licensing info.
#
# Lint All The Things!
#
# Should be run from the lint directory
# Exit on error immediately
set -e
cd ..
verilator -DSIMULATION -DVERILATOR --lint-only -Wall -f lint/filelist.f -top letc_top --waiver-output lint/waivers.txt

@ -81,7 +81,7 @@ fifo_0r1w #(
.i_push(from_manager.awvalid),
.o_full(awfifo_full),
.i_wdata(aw_from_manager),
//Read port (0-cycle latency)
.i_pop(to_subordinate.awready),
.o_empty(awfifo_empty),
@ -129,7 +129,7 @@ fifo_0r1w #(
.i_push(from_manager.wvalid),
.o_full(wfifo_full),
.i_wdata(w_from_manager),
//Read port (0-cycle latency)
.i_pop(to_subordinate.wready),
.o_empty(wfifo_empty),
@ -173,7 +173,7 @@ fifo_0r1w #(
.i_push(to_subordinate.bvalid),
.o_full(bfifo_full),
.i_wdata(b_from_subordinate),
//Read port (0-cycle latency)
.i_pop(from_manager.bready),
.o_empty(bfifo_empty),
@ -224,7 +224,7 @@ fifo_0r1w #(
.i_push(from_manager.arvalid),
.o_full(arfifo_full),
.i_wdata(ar_from_manager),
//Read port (0-cycle latency)
.i_pop(to_subordinate.arready),
.o_empty(arfifo_empty),
@ -274,7 +274,7 @@ fifo_0r1w #(
.i_push(to_subordinate.rvalid),
.o_full(rfifo_full),
.i_wdata(r_from_subordinate),
//Read port (0-cycle latency)
.i_pop(from_manager.rready),
.o_empty(rfifo_empty),

@ -39,7 +39,7 @@ module fifo_0r0w #(
input logic i_push,
output logic o_full,
input logic [DWIDTH-1:0] i_wdata,
//Read port (0-cycle latency)
input logic i_pop,
output logic o_empty,
@ -66,7 +66,7 @@ always_comb begin
o_full = (next_push_idx == pop_idx) & ~i_pop;//Next push would make it indistinguishable from empty
o_empty = (push_idx == pop_idx) & ~i_push;//If we are pushing we can forward the data, so we are not empty
if (i_push & i_pop & (push_idx == pop_idx)) begin
o_rdata = i_wdata;//Forward data to get the effective 0-cycle write latency
end else begin

@ -36,7 +36,7 @@ module fifo_0r1w #(
input logic i_push,
output logic o_full,
input logic [DWIDTH-1:0] i_wdata,
//Read port (0-cycle latency)
input logic i_pop,
output logic o_empty,

@ -36,7 +36,7 @@ module fifo_1r1w #(
input logic i_push,
output logic o_full,
input logic [DWIDTH-1:0] i_wdata,
//Read port (0-cycle latency)
input logic i_pop,
output logic o_empty,

@ -628,4 +628,4 @@ assign led0_b_sync = btn_sync[0];
assign led1_b_sync = btn_sync[1];
*/
endmodule
endmodule : coraz7_top

@ -22,7 +22,7 @@ module letc_core_cache
//Cache interface
letc_core_cache_if.cache cache_if,
//LIMP interface
letc_core_limp_if.requestor limp
);

@ -29,51 +29,6 @@ module letc_core_csr
//Interface for CSRs whose state (at least partially) exists outside of this module
//TODO
/*
input logic [11:0] csr_sel,//TODO should we make an enum for this?
output word_t csr_data_out,
//Privilege mode
output prv_mode_t prv_mode_ff,
input prv_mode_t prv_mode_wd,
input logic prv_mode_we,
//Implicitly read CSRs (ordered by address ascending)
//TODO move these into a struct
output word_t csr_sie_ff,
output word_t csr_stvec_ff,
//TODO sip?
output word_t csr_satp_ff,
output word_t csr_mstatus_ff,
output word_t csr_medeleg_ff,
output word_t csr_mideleg_ff,
output word_t csr_mie_ff,
output word_t csr_mtvec_ff,
//TODO mip?
//TODO minst?
//TODO others
//Implicitly written CSRs (ordered by address ascending)
//TODO move these into a struct
input word_t csr_sepc_wd,
input logic csr_sepc_we,
input word_t csr_scause_wd,
input logic csr_scause_we,
input word_t csr_stval_wd,//TODO maybe not have this?
input logic csr_stval_we,//TODO ^
//TODO sip?
input word_t csr_mstatus_wd,//TODO this likely needs to be broken into its individual fields
input logic csr_mstatus_we,
input word_t csr_mepc_wd,
input logic csr_mepc_we,
input word_t csr_mcause_wd,
input logic csr_mcause_we
//TODO mtval?
//TODO mip?
//TODO minst?
//TODO others
*/
//CSR explicit software read interface
input logic i_csr_explicit_ren,
input logic [11:0] i_csr_explicit_raddr,

@ -21,7 +21,7 @@ module letc_core_mmu
input logic i_rst_n,
//TODO design MMU interfaces
//LIMP interface
letc_core_limp_if.requestor limp
);

@ -124,7 +124,7 @@ typedef enum logic [1:0] {
} alu_op2_src_e;
/* ------------------------------------------------------------------------------------------------
* Pipeline Datapath Structs
* Pipeline Datapath Structs
* --------------------------------------------------------------------------------------------- */
typedef struct packed {
@ -195,7 +195,7 @@ typedef struct packed {
} e2_to_w_s;
/* ------------------------------------------------------------------------------------------------
* CSR Structs
* CSR Structs
* --------------------------------------------------------------------------------------------- */
//Note: Only provides CSRs that actually need to be implicitly read by LETC Core logic

@ -34,7 +34,7 @@ module letc_core_rf
//rs1 Read Port
input reg_idx_t i_rs1_idx,
output word_t o_rs1_rdata,
//rs2 Read Port
input reg_idx_t i_rs2_idx,
output word_t o_rs2_rdata

@ -31,7 +31,7 @@ module letc_core_stage_e2
//From E1
input e1_to_e2_s i_e1_to_e2,
//To W
output e2_to_w_s o_e2_to_w
);

@ -30,9 +30,9 @@ module letc_core_stage_w
input logic i_stage_stall,
//rd Write Port
output reg_idx_t i_rd_idx,
output word_t i_rd_wdata,
output logic i_rd_wen,
output reg_idx_t o_rd_idx,
output word_t o_rd_wdata,
output logic o_rd_wen,
//CSR Write Port
output logic o_csr_explicit_wen,

@ -235,9 +235,9 @@ letc_core_stage_w stage_w (
.i_stage_stall(stage_stall[5]),
//rd Write Port
.i_rd_idx(rd_idx),
.i_rd_wdata(rd_wdata),
.i_rd_wen(rd_wen),
.o_rd_idx(rd_idx),
.o_rd_wdata(rd_wdata),
.o_rd_wen(rd_wen),
//CSR Write Port
.o_csr_explicit_wen(csr_explicit_wen),
@ -251,7 +251,7 @@ letc_core_stage_w stage_w (
letc_core_tghm tghm (
.*,
//Interrupts
//Passed through via .* above

@ -46,7 +46,7 @@ always_comb begin
default_sub.wlast = core.wlast;
default_sub.wid = core.wid;
core.wready = default_sub.wready;
core.bvalid = default_sub.bvalid;
core.bresp = default_sub.bresp;
core.bid = default_sub.bid;

@ -23,7 +23,9 @@ set OUTPUT_DIR ./
set RTL_TOP coraz7_top
set CONSTRAINTS_SOURCE $FC_ROOT/constraints.xdc
set RTL_SOURCE "
$RTL_ROOT/common/fifo/fifo_0r0w.sv
$RTL_ROOT/common/fifo/fifo_0r1w.sv
$RTL_ROOT/common/fifo/fifo_1r1w.sv
$RTL_ROOT/common/cdc/cdc_synchronizer.sv
$RTL_ROOT/common/axi/axi_pkg.sv
$RTL_ROOT/common/axi/axi_if.sv
@ -41,6 +43,14 @@ set RTL_SOURCE "
$RTL_ROOT/letc/core/letc_core_stage_e1.sv
$RTL_ROOT/letc/core/letc_core_stage_e2.sv
$RTL_ROOT/letc/core/letc_core_stage_w.sv
$RTL_ROOT/letc/core/letc_core_tghm.sv
$RTL_ROOT/letc/core/letc_core_cache.sv
$RTL_ROOT/letc/core/letc_core_tlb.sv
$RTL_ROOT/letc/core/letc_core_mmu.sv
$RTL_ROOT/letc/core/letc_core_csr.sv
$RTL_ROOT/letc/core/letc_core_limp_if.sv
$RTL_ROOT/letc/core/letc_core_cache_if.sv
$RTL_ROOT/letc/core/letc_core_tlb_if.sv
$RTL_ROOT/letc/core/letc_core_axi_fsm.sv
$RTL_ROOT/letc/matrix/letc_matrix_top.sv

Loading…
Cancel
Save