Begin setting things up

main
John Zacarias Jekel 2 years ago
parent 466f8f7057
commit 0c2bd554ef
  1. 21
      .gitignore
  2. 24
      rtl/zacore/zacore_top.sv
  3. 13
      tb/zacore_sb.sh
  4. 70
      tb/zacore_tb.cpp
  5. 32
      tb/zacore_tb.sv

21
.gitignore vendored

@ -0,0 +1,21 @@
#Gitignore borrowed from jzjcore
#unused/awful quartus stuff
simulation
*.bak
.qsys_edit
#Don't need to be distributed because they are easily generated from other files
*.vcd
output_files
incremental_db
db
*.qws
*.o
*.bin
*obj_dir*
#Other things
*.kate-swp
*.autosave.xopp

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module zacore_top #(
) (
input logic i_clk,
input logic i_rst,//Synchrenous
//Memory interface
output logic o_fetch_req,
output logic o_read_req,
output logic o_write_req,
output logic [31:0] o_fetch_addr,
output logic [31:0] o_data_addr,
output logic [31:0] o_data_write,
output logic [3:0] o_data_write_mask,//Only write a byte if the corresponding bit is set (bit 0 is the LSB, bit 1 is byte 1, and so on)
input logic [31:0] i_data_read
)
endmodule//zacore_top

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#!/bin/bash
FILES_TO_INCLUDE="-I ../rtl/zacore/zacore_top.sv"
#Verilate the testbench and vgacpu SystemVerilog files//todo split into multiple commands
verilator $FILES_TO_INCLUDE --timescale 10ns/10ns -Wall -Wno-fatal -sv -cc zacore_tb.sv --exe --trace-fst -O3 --top-module zacore_tb +1800-2017ext+sv --build zacore_tb.cpp
#Run the simulation (creates /tmp/vgacpu_verilator.vcd)
(cd ../../ && ./tb/verilator/obj_dir/Vvgacpu_verilator)
#Open in waveform viewer
gtkwave /tmp/zacore_tb.vcd
#Delete files
rm -rf ./obj_dir
rm /tmp/zacore_tb.vcd

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/* verilator.cpp
* By: John Jekel
*
* Verilator testbench for vgacpu
*
* Based on the one from JZJCoreF
*
*/
/* Includes */
#include <cstdint>
#include "verilated.h"
//The header that will be generated by verilator
#include "Vzacore_tb.h"
/* Variables */
static uint64_t simulation_time = 0;//Used to keep track of simulation time for dumping a wave file
/* Function Declarations */
double sc_time_stamp();//Used by Verilator to keep track of simulation time dumping a wave file
/* Function Implementations */
int main(int argc, char** argv) {
//Initialization for verilator
Verilated::commandArgs(argc, argv);//Interpret command line arguments for Verilator
Vzacore_tb* testbench = new Vzacore_tb;//Instantiate the zacore_tb module for simulation
Verilated::traceEverOn(true);//Needed to support dumping
//Simulation
testbench->eval();//Update simulation
++simulation_time;//Increment time counter
//Reset all registers
testbench->i_rst = 1;
testbench->eval();//Update simulation
++simulation_time;//Increment time counter
testbench->i_clk = 1;//Set clock high
testbench->eval();//Update simulation
++simulation_time;//Increment time counter
testbench->i_clk = 0;//Set clock low
testbench->eval();//Update simulation
++simulation_time;//Increment time counter
testbench->i_rst = 0;
testbench->eval();//Update simulation
++simulation_time;//Increment time counter
//Toggle the clock repeadetly
while (!Verilated::gotFinish()) {//Run simulation until $finish() is called in SystemVerilog
testbench->i_clk = 1;//Set clock high
testbench->eval();//Update simulation
++simulation_time;//Increment time counter
testbench->i_clk = 0;//Set clock low
testbench->eval();//Update simulation
++simulation_time;//Increment time counter
}
//Cleanup and exit
delete testbench;
return 0;
}
double sc_time_stamp() {//Callback used by Verilator for dumping (it expects this symbol)
return (double)(simulation_time);
}

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module zacore_tb (
input logic i_clk,
input logic i_rst,
);
logic o_fetch_req;
logic o_read_req;
logic o_write_req;
logic [31:0] o_fetch_addr;
logic [31:0] o_data_addr;
logic [31:0] o_data_write;
logic [3:0] o_data_write_mask;
logic [31:0] i_data_read;
zacore_top top (.*);
initial begin
$dumpfile("/tmp/zacore_tb.vcd");
$dumpvars(0, zacore_tb);
end
//Clock cycle counter to end simulation
logic [63:0] counter = 0;
always_ff @(posedge clk) begin
counter <= counter + 1;
if (counter == 1000000)
$finish();
end
endmodule
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